The present invention relates generally to the testing of integrated circuits. More specifically, in one embodiment, the invention provides an improved computer simulation model of an integrated circuit testing system.
With the high level of complexity of modern integrated circuits, it is becoming increasingly difficult to test integrated circuits to ensure that they were manufactured with no defects. Typically, a device under test ("DUT") is tested by applying predetermined test waveform patterns its input pins. A tester generates the waveforms and monitors the DUT's output pins to ensure that the device operates as expected.
Often, the waveform patterns needed to adequately test the DUT are complex. Consequently, long lead times are needed to generate the waveform patterns and determine what results to expect on the output. Waiting for the first device to be manufactured for the waveform patterns and expected results to be tested is inefficient and costly.
To overcome this inefficiency, manufacturers have created software simulation models of the DUT and the tester to verify the accuracy of the waveforms before having physical parts available on which to test them. The waveforms may be applied to the software models, and the engineer can experiment and work the bugs out of the testing package before applying the waveforms to a physical device. This decreases the time it takes to perform the tests after manufacture of the devices, and prevents damage to the physical device by ensuring that the tester does not drive signals inappropriately.
Because of design considerations, a purchaser of an integrated circuit will sometimes prefer a package which has a fewer number of physical pins than are provided in a standard integrated circuit package. However, for ease of manufacturing, creating a different die for each of these customers may not be desirable for the manufacturer. Instead, the manufacturer often uses a common die, but places it in a package with fewer physical pins. Consequently, only a portion of the pads on the die are connected to a package pin. A fully-bonded package is one in which all pads on the die are connected to a package pin. A downbond is one in which only a subset of the pads are connected to a package pin.
In the past, these downbonds created a problem for the computer models used in the simulation of the devices. When a downbond was to be tested, a person running the test had to manually define which pins of the DUT model to connect to which pins of the tester. Therefore, each time a different downbond was tested, different connection had to be determined and waveform patterns had to be adjusted to correspond with the pin configuration of the new downbond. This method introduced the possibility of error, and was very time-consuming.
Accordingly, an improved method for simulating a device under test is desirable.